The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure including an n-type field effect transistor (nFET) containing vertically stacked and suspended Si channel material nanosheets stacked vertically above a p-type field effect transistor (pFET) containing vertically stacked and suspended SiGe channel material nanosheets, and a method of forming the same.
The use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (FinFETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. One type of non-planar semiconductor device that has been touted as a viable option beyond the 7 nm technology node is a nanosheet containing device. By “nanosheet containing device” it is meant that the device contains one or more layers of semiconductor channel material portions having a vertical thickness that is substantially less than its width.
Also, three dimensional (3D) integration by vertically stacking nFETs and pFETs is an attractive approach for 3 nm node and beyond area scaling. Such vertically stacking of nFETs and pFETs combined with nanosheet technology can benefit from device electrostatics control in addition to area scaling. The threshold voltage control of nFETs and pFETs with a single work function metal is difficult as both the nFETs and pFETs have a Si channel. There is thus a need to provide vertically stacked dual channel nFETs and pFETs which can provide low threshold voltage and a single work function metal.